`timescale 1ns/1ps
module CredentialMemory(PC, PCE, RC, RCE, RME, rst, clk, CardSwipe, CredI, CredRetO, Access);
input [23:0] PC;              //Program Credential
input PCE;                    //Program Credential Enable
input [23:0] RC;              //Remove Credential
input RCE;                    //Remove Credential Enable
input RME;                    //Return Memory Enable
input rst;                    //reset
input clk;                    //clock
input CardSwipe;              //Card swipe
input [23:0] CredI;           //Input Credential
output [23:0] CredRetO;       //Credential Return Out
output Access;                //Access

wire [23:0] PC;
wire PCE;
wire [23:0] RC;
wire RCE;
wire RME;
wire CardSwipe;
wire [23:0] CredI;
reg [23:0] CredRetO;
reg Access;
reg [23:0] mem [99:0];
reg [7:0] i;

always @ (posedge clk or posedge rst)
begin
  if(rst == 1'b0) begin
    for(i = 0; i < 100; i = i + 1) begin
    mem[i] = 24'b1;
    end
  end else begin
    if(RME == 1'b1) begin
      for(i = 0; i < 100; i = i + 1) begin
        CredRetO <= mem[i];
      end
    end else if(PCE == 1'b1) begin
      while(i < 100 && mem[i] != 24'b1) begin
        i = i + 1;
      end
      mem[i] = PC;
    end else if(RCE == 1'b1) begin
      while(i < 100 && mem[i] != RC) begin
        i = i + 1;
      end
      mem[i] = 24'b1;
    end else if(CardSwipe == 1'b1) begin
      while(i < 100 && mem[i]!= CredI) begin
        i = i + 1;
      end
      if(i < 100) begin
        Access = 1'b1;
      end
      else begin
        Access = 1'b0;
      end
    end else begin
      // do nothing
    end
  end
end

endmodule

